1. Field of the Invention
The present invention relates to an article of manufacture for forming leads to interconnect semiconductor die with the next level of electronics packaging and a process for manufacturing the same.
2. Background of the Invention
The term interconnects herein refers to the electrical connections between a semiconductor die and the next level of microelectronics packaging, such as lead frames, chip carriers, ceramic substrates, printed circuit boards, etc. Historically this first-level interconnect has been achieved using very fine gold or aluminum wire. Other methods of first-level interconnection which have been used somewhat successfully include processes known as Controlled Collapse Solder Bump, Flipchips, Beam Leads, and "TAB" (Tape for Automated Bonding).
This invention expands the field for successful utilization of TAB. TAB in general consists of a very thin copper foil processed to produce a pattern of copper leads or traces which can be used in the same manner as gold or aluminum wires to form interconnections between the semiconductor die and the next level of microelectronic packaging.
A semiconductor die typically has interconnect pads exposed on its surface. These pads, called I/O (input/output) pads, are typically termination conductive pads of the aluminum traces which carry the electrical signals internal to the semiconductor die. The surface of the semiconductor die is protected with a very thin passivation layer made for example of silicon dioxide, silicon nitride, or other inert dielectric materials, with windows or vias exposing the I/O pads.
On these semiconductor I/O pads, the gold, aluminum, or copper leads are bonded to form an "innerlead bond". The gold, aluminum, or copper leads are also bonded to the next level of microelectronic packaging and this is termed "the outerlead" bond, completing the electrical interconnection.
TAB has been an attractive alternative to gold and aluminum wire bonding in that it consists of a continuous tape of patterns of copper leads, each pattern corresponding to the pattern of I/O pads on the surface of the semiconductor die. This continuous tape has sprocket hole patterns along its edge, much like a motion picture film strip, allowing an automated transport of the tape across the bonding location where the semiconductor die is accurately positioned, and in one step all the copper leads are "innerlead" bonded to the semiconductor die. The semiconductor die at that point is lifted from the bonding location and becomes part of the continuous tape.
Many times it is desirable to electrically test the semiconductor die after the innerlead bonds are made but before the die is permanently attached to its next level of packaging. Such testing is possible using a type of TAB tape on which the conductor pattern consists of electrically isolated copper leads with large test pad areas for each lead and a dielectric film under the conductor pattern for support during bonding and testing. After the innerlead bonds are made, the test pads can be contacted to electrically test the die and the innerlead bonds before the outerlead bonds are made. After testing, the continuous tape with the "innerlead" bonded semiconductor die is then fed across a second bonding location where the copper leads, typically in one operation, are excised from the continuous tape, formed if desired, and "outerlead" bonded to the next level of packaging.
Prior art TAB tapes having dielectric support have been manufactured so that the dielectric support has been formed in an essentially continuous film bonded to the metal leads with the interface between the metal leads and dielectric support being essentially continuous and planar. These TAB tapes have been made by bonding a tape of dielectric support with an adhesive to a tape of metal lead patterns with holes punched in the dielectric for sprockets and for allowing access to the leads for bonding. Alternatively, the dielectric support has been formed on the metal leads by casting a continuous liquid dielectric film over a planar metal tape and then photolithographically etching the lead pattern into the metal tape. Yet another prior art method involves using an electroless copper deposition technique to apply a very thin layer of copper to a planar dielectric film tape which is then photolithographically processed so that the desired lead pattern can be pattern plated, or the entire surface of one side of the dielectric is electroplated to the desired thickness and then photolithographically processed so that the desired lead pattern can be etched into the electroplated metal, typically copper metal. In each of the last three processes, a photolithographic process is required so that certain areas of the dielectric film can be etched so as to open either sprocket holes and/or areas where the copper metal is accessible through the dielectric.
Advantages of TAB, besides providing the capability of testing the innerlead bonds, include greater bond strengths, greater lead strengths, improved thermal dissipation and higher conductivity because TAB leads generally have greater cross-sectional area and bonding area than do fine wire leads for comparable bonding environments. Further, the manufacture of TAB leads allows greater control over the patterns of the leads providing greater design flexibility in the semiconductor die since the TAB leads can bond to I/O pads which are smaller and closer together than has been possible using wire bonding techniques.
However, when TAB is used, because I/O pads on the semiconductor die are somewhat recessed below the surface of the passivation layer, it is necessary to provide a conductive mechanical stand-off, called a "bump", between the I/O pad on the die and the lead of the TAB tape. Without this bump, there is a danger of cracking the passivation layer on the die and destroying its functionality when the lead is bonded to the pad, and/or a danger of the leads contacting the exposed edge of the die and thereby creating electrical shorts.
These bumps can be processed onto the die before the dies are separated out of the wafer form. This typically involves various layers of thin film metal depositions over the entire wafer to provide adhesion to the surface of the wafers, a thermal diffusion barrier, and a plateable surface. Then, using a photolithographic process, electroplated bumps are formed, typically of gold, over the I/O pads. A final step involves the removal of the thin film metal deposition layers that are exposed everywhere but under the electroplated bumps. These electroplated bumps can now be innerlead bonded to flat, or planar, TAB copper leads. If the bump is of gold plating, the copper leads of the TAB tape are typically plated with a very thin layer of tin or gold, to allow the formation of a gold-tin eutectic bond or a gold-gold thermocompression bond. Other metallurgies are also used. However, dies with "bumps" formed on the pads are available only to those companies that have control of the wafer fabrication, which is not typically the case. Therefore, alternative bumping techniques are needed to process the bumps as part of the metal leads of the TAB tape. Such techniques include selectively etching the metal to form the bumps on the innerlead tips of the copper leads or photolithographically processing the copper leads to allow the electroplating of bumps onto the innerlead tips of the copper leads. These techniques are entirely practical and are being utilized in commercial applications.
However, these bumping processes have not been successfully applied to TAB tape using dielectric support for electrical isolation and thus testing of the leads after innerlead bonding. This is due in great part to the difficulties in processing either a selectively etched or electroplated bump on the innerlead tips of the metal leads while there is a continuous film of dielectric support material adjacent to one side of a continuous metal film.
In sum, prior art technology provides a utilization of non-testable TAB tape where a bumped semiconductor die is innerlead bonded with a non-bumped planar all copper TAB tape, or a non-bumped semiconductor die is innerlead bonded with a bumped all copper TAB tape. Testable TAB can be used on a bumped semiconductor die that is innerlead bonded with a non-bumped planar TAB tape which has copper leads supported on a dielectric film.
To expand the field of successful utilization of testable TAB tape, there is a need for a process for manufacturing a TAB tape which overcomes the difficulties of having a continuous dielectric film mated to a continuous metal film along a planar interface and a further need for a testable bumped TAB tape.